This invention relates to memory flow control in a microprocessor-based system having embedded DRAM. More particularly, this invention relates to a switch-based controller for memory requests in a microprocessor-based system having multiple DRAM banks.
It is becoming increasingly common to provide integrated circuit devices having both logic and DRAM memory on-board; such devices are known as xe2x80x9cembedded DRAMxe2x80x9d devices. Such devices can include complete or nearly complete microprocessor systems, with the microprocessor and other logic (e.g., coprocessors, I/O controllers, etc.), as well as multiple banks of DRAM, all included on the same chip or on chips within the same chipset.
Those various logic and embedded DRAM components could communicate just as they do in systems in which they are provided as discrete devicesxe2x80x94i.e., using a bus architecture. However, in a bus architecture, only one device can use the bus at a time, which causes a bottleneck that affects data throughput. Moreover, with embedded devices, there are no external interfaces that would constrain one to use a bus architecture. Therefore, a need exists for a faster system and method for communication between logic devices and DRAMs embedded therewith.
In accordance with the present invention, the standard bus architecture for communicating between various banks of memory and various system resources is replaced by a switch-based architecture. The switch receives memory requests from system resources and relays each request to the appropriate bank of memory when that bank indicates that it is not busy. When the bank of memory returns the result of the request, the switch establishes a connection between that bank of memory and the system resource that made the request, as soon as that resource is also free. While the invention is particularly useful in systems in which the memory banks are embedded DRAM memory, it is also applicable where any one or more of the memory banks and other system resources are discrete devices.
In order to facilitate the routing of requests and returned data by the switch to the appropriate memory bank or system resource, each request preferably includes both a source tag and a destination tag. The destination tag is applied to a request by the system resource making the request. The source tag also may be applied to the request by the system resource making the request, but alternatively may be applied by the switch, which knows the identity of the resource by virtue of the requestor port through which the system resource is attached to the switch.
Similarly, each memory bank is attached to the switch through a respective memory port. When a memory bank returns the result of a memory request, the identity of the memory bank is preferably ascertained based on the memory port to which it is attached. The destination system resource for the result can be indicated by a destination tag applied by the local controller of the memory bank, or the switch can keep track of which memory requests have been routed to which memory banks and which resources made the requests, so that when a particular memory bank returns its result, the switch xe2x80x9cknowsxe2x80x9d which system resource made the request that that memory bank was working on, and therefore to which system resource the result should be returned.
Thus, in accordance with the invention, a computer system is provided having a plurality of banks of memory and a plurality of system resources that submit memory requests to the memory. The system is preferably a single chip having both logic and embedded memory, particularly DRAM memory. A switch interconnects the plurality of banks of memory and the plurality of system resources, and establishes communications between (a) a respective one of the resources, and (b) a respective one of the banks of memory of which the respective one of the resources makes a request. The connection is not established until the respective one of the resources and the respective one of the banks of memory are both available. The switch architecture allows multiple connections to exist between different memory port/requester port pairs, although at any one time, each memory port can be connected to only one requester port and vice-versa.